Differential read schemes with local and global sense amplifiers are quite common in static RAMs. Implementing a differential read scheme in a register file having a large number of registers, where each register is multi-ported, presents, additional difficulties if differential sense amplifiers are used due to the efforts required to design these sensitive circuits.
Implementing a single ended read scheme is difficult due to the large number of register cells attached to each bit line which results in excessive device load due to the read access transistors' drain capacitance and the high interconnect resistance and capacitance due to the length of a bit line.
Accordingly, a simple and robust scheme for reading a multi-port register file is required.